1. Field of the Invention
The present invention relates to a circuit for comparing the magnitude of digital values.
2. Description of the Related Art
Various digital circuits use a circuit for comparing digital values as shown, for example, TEXAS INSTRUMENTS, ADVANCED BIPOLAR LOGIC FAMILY DATA BOOK, p.p. 4-658.about.4-665, 1990. One of such comparator circuits, for example, has a configuration as shown in FIG. 4. This circuit is for comparing the magnitude of values of digital signals A and B expressed in n-bit binary signals applied to terminals 40 and 42.
In this circuit, the digital signal A applied to the terminal 40 is supplied to an adder-subtractor circuit 44. The digital signal B applied to the terminal 42, on the other hand, is supplied to a complementation circuit 46 for converting the supplied signal to a complement of 2n. This conversion to a complement can be effected by inverting the binary signal "0" to "1" and "1" to "0" of each bit of a n-bit digital signal, adding "1" to the result of inversion, and deleting "1" which may be carried to the order of 2.sup.n. The adder-subtractor 44 adds the digital signal A and the complement of the digital signal B to each other, and produces "A-B". A decision circuit 48 decides that A&gt;B, when the "A-B" is positive, and that A&lt;B, when "A-B" is negative, and produces an output indicating the result of decision.
The conventional digital value comparator circuits including the one illustrated in FIG. 4 are configured of gate circuits in multiple stages. A signal is delayed each time it passes a gate circuit. A considerable delay, therefore, is unavoidable due to accumulation of delays before the final result of comparison is obtained after application of signals to be compared. Especially when using an adder-subtractor of a ripple carry type as the adder-subtractor 44 in FIG. 4, it takes a considerable time to transmit the carry information from the least significant bit to the most significant bit of the adder, thereby leading to disadvantage that the delay time is greatly increased with the number of bits.
Also, in the digital value comparator circuit shown in FIG. 4, the complementation circuit 46 and the decision circuit 48 require almost as many transistors as the number of bits of the digital value to be compared, and in addition, more than ten transistors per bit are required for making up the adder-subtractor circuit. For this reason, the number of all transistors required greatly increases as the number of bits of the digital value increases. Since the space occupied by large scale integration of the circuit elements increases greatly with the increase in the number of transistors as described above, high density and high integration are hampered.